1. Field of the Invention
The present invention relates to a technique for protection of a CMOS circuit on bulk silicon from "latch-up" of intrinsic parasitic devices in the CMOS structure. More specifically, the present invention is related to a circuit for detecting the excess currents characteristic of latch-up of an intrinsic parasitic SCR device, terminating the latch-up condition by current starving the SCR device and re-establishing normal circuit operation after the latch-up condition has been terminated.
2. Background of the Invention
A common problem in CMOS circuits constructed on bulk silicon, and in many other triple diffused integrated circuits as well, is the disruption of normal circuit operation and possible destruction of the chip itself as a result of the latch-up of a parasitic SCR device. See for instance "Latch-up in CMOS Integrated Circuits" by B. L. Gregory and B. D. Shafer in the IEEE trans. NUCL sci., Volume NS-20, p. 293, 1973. A cross section of a typical CMOS circuit is illustrated in FIG. 1, which illustrates a pair of parasitic transistors in an SCR configuration inherent in the construction of this triple diffused CMOS structure. A detailed schematic diagram of the parasitic SCR circuit is illustrated in FIG. 2. Particularly, in typical CMOS circuits such as digital logic circuits, interconnects typically couple the base of parasitic device Q1 to the positive power supply V+ by coupling N.sup.- substrate 10 to the V+ power supply via N+ diffused region 20. The base of parasitic device Q2 is effectively coupled to the negative power supply V.sup.- by coupling the P.sup.- diffused region 30 to the negative power supply V.sup.- via P.sup.+ diffused region 40. These connections normally bias the parasitic SCR circuit off. Thus, unless a starting current is forced into the base of one of the parasitic devices, this parasitic SCR circuit will remain off. In normal circuit operation, this parasitic SCR is never intentionally activated. However, it is possible to unintentionally activate the SCR in a number of ways. Referring to the circuit schematic in FIG. 2 of the parasitic SCR, the inherent resistance of P.sup.- region 30 (known as the well) is modeled as resistor R.sub.well and the inherent resistance of N.sup.- substrate 10 is modeled as resistor R.sub.sub. A current flowing in P.sup.- region 30 can cause a voltage to be established across the resistor R.sub.well. If this voltage is sufficient to forward bias the junction between well 30 and N+ region 50, parasitic device Q2 is activated and draws current from N.sup.- substrate 10. If this current establishes a voltage drop across the resistor R.sub.sub sufficient to forward bias a junction between a P+ region 60 and N.sup.- substrate 10, parasitic transistor Q1 is activated. Transistor Q1 will supply excess current to the base of transistor Q2 and cause the parasitic SCR circuit to latch-up if the feedback current gain of the parasitic SCR circuit is greater than one. This latch-up may induce the latch-up of additional parasitic SCR devices in a CMOS circuit. The latch-up of one or more parasitic SCR devices provides a low impedance current path between the positive and negative power supplies which typically draws several amps of current. This latch-up current is often sufficient to cause the thermal destruction of a portion of the integrated circuit which may render the entire circuit inoperative.
SCR action may be initiated by the external overdriving of circuit nodes, device avalanche, photo-currents or internal charge pumping. Typically, SCR latch-up is often initiated during a power-up sequence of a CMOS circuit since the exact relationships between the power supplies and the inputs are not always carefully specified or controlled.
Conventionally, layout or process modifications have been used to decrease the probability of any of these mechanisms leading to the catastrophic latch-up of bulk CMOS circuits. However, these layout and process modifications involve either increased process complexity or decreased circuit density.
A number of different layout related techniques have been employed to prevent parasitic SCR action. For instance, the substrate and well contacts, regions 20 and 40 in FIG. 1, can be placed frequently on the chip to minimize accumulated voltage drops across inherent resistors to reduce the probability of forward biasing one of the parasitic junctions. Another method is to fully guard-band input protection diodes and output drivers to minimize the bi-polar action and to isolate internal circuits with series resistors whenever possible. Another method involves placing resistors in series with the supply lines which has the effect of increasing the required trigger voltage and current starving the SCR once it is triggered. However, this latter technique is not generally useful since many circuits such as output drivers require a low impedance supply voltage.
Process related techniques to minimize SCR action have also been employed. In one technique a buried layer is placed under portion of the chip to minimize the inherent IR voltage drops and to reduce the beta (B) of the parasitic bipolar transistors. In another technique a deep isolation diffusion is placed around the wells to reduce lateral bi-polar action. Another technique, taught by Dawes et al., in "Process Technology Radiation-Hardened CMOS Integrated Circuits" in the IEEE Journal of Solid State Circuits Vol SC-11, No. 4, August 1976, reduces the bulk carrier lifetime by gold doping the silicon substrate. This doping reduces the gain of the bi-polar devices, thus the likelihood of SCR latch-up. In another technique an insulating sapphire substrate eliminates the SCR circuit paths altogether.
However, many of these techniques merely reduce the probability of a catastrophic SCR latch-up occurring. Further, these techniques involve either additional complexity in the layout of the production process or limitations on circuit density.